Lattice公司的MachXO系于是非易失可无限次配置的可编程逻辑器件(PLD),具有256到2280个LUT,I/O数多达271个,多达27.6Kb sysMEM嵌入区块RAM(EBR)和多达7.7Kb的分布式RAM,支持IEEE 标准1149.1 边界扫描,工作电压而不服.3V,2.5V,1.8V或1.2V.主要用在低密度的工业控制,医疗电子,汽车电子,通信和消费电子等领域.本文介绍了MachXO 系列主要特性以及MachXO™ Mini 开发套件主要特性与MachXO™ Mini评估板方框图,电路图和材料清单.
The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device.
Designed for a broad range of low density applications including system control designs, the MachXO PLD family is used in a variety of end markets including consumer, automotive, communications, computing, industrial and medical.
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