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MicrosemiDS0142IEEE 1588定时同步模块解决方案

Microsemi公司的DS0142是IEEE 1588定时同步模块,提供高性能时钟同步功能,以满足频率精度,电信频率掩码和相位与时间对准要求,满足ITU-T分组时钟规格或分组时钟规范草案,如ITU-T G.8261 Appendix VI和ITU-T G.8263 PEC-S等,以及ITU-T G.8273.4 T-BC-P(草案)等,主要用在移动基础设备如GSM, WCDMA, TD-SCDMA, LTE和LTE-A,企业基础设备,工业以太互联网,国防和智能能源.本文介绍了DS0142主要特性和框图,应用架构图和软件架构图,以及定时同步模块电路图.

The IEEE 1588 timing synchronization module provides high-performance clock synchronization capableof meeting frequency accuracy, telecom frequency masks, and phase and time alignment requirementsfor the telecom industry, including mobile backhaul for GSM, WCDMA and LTE applications. The timingsynchronization module meets performance requirements of ITU-T packet clock specifications, or draftpacket clock specifications, including:

• ITU-T G.8261 Appendix VI
• ITU-T G.8263 PEC-S
• ITU-T G.8273.2 T-BC
• ITU-T G.8273.2 T-TSC
• ITU-T G.8273.4 T-BC-P (draft)
• ITU-T G.8273.4 T-TSC-A (draft)
• ITU-T G.8273.4 T-TSC-P (draft
The timing synchronization module is suitable for use in a wide variety of markets and applications,including the following IEEE 1588-2008 Profiles:
• Annex J.3 Delay Request-Response Default Profile
• Annex J.4 Peer-to-Peer Default Profile
• ITU-T G.8265.1 Telecom Profile for Frequency Synchronization
• ITU-T G.8275.1 Telecom Profile for Phase with Full Timing Support Networks
• ITU-T G.8275.2 Telecom Profile for Phase with Partial Timing Support Networks
The timing synchronization module is controlled by a very simple CLI interface over a UART serialinterface or ethernet port.
The timing synchronization module has inter-operable interfaces to a motherboard:
• Two UART serial ports: One for host control, one for NMEA-0183
• One ethernet SGMII port: For traffic and host control
• Seven clock inputs
• Five Clock (singled-ended) and Five Clock (differential) outputs
• One system clock TCXO/OCXO input
• JTAG port
• Power rails (1.0V, 1.2V, 1.8V, 2.5V, 3.3V)

DS0142主要特性:

IEEE 1588-2008 Synchronization
• Operation as BC and OC-Slave
• Default Profile, Telecom Profile for Frequency andTelecom Profile for Phase
BC Operation
• Synchronize with a GM and connect downstream toup to 4 OC-clients
• Redundant master / source supported.
For instance, if IEEE1588 link fails, BC engine canbe synced to GNSS input or SyncE input.
Contact factory for solutions to support 128 or up to1024 clients
OC-Slave Operation
• Synchronize with a GMRedundant master / sourcesupported. For instance, if IEEE1588 link fails, OCcan be synced to GNSS input or SyncE input whenavailable
• Holdover when all inputs are lost
Packet Synchronization Support
• FDD ±15 ppb
• MTIE G.823/T1.101 sync mask
• TDD ±1 μs
• ITU-T G.8263, G.8273.2, G.8273.4 (draft)
Physical Synchronization Support
• Two independent clock engines, configurable forIEEE 1588, GNSS or SyncE operation
• Digital PLLs programmable bandwidth from 0.1 mHzup to 1 kHz
• Any input clock rate from 1 Hz to 750 MHz
• Any output clock rate from 1Hz to 750MHz
• Output jitter below 0.61 psrms
Synchronous Ethernet and Performance
• Full support reference monitoring, referenceswitching, holdover, T0/T4
• G.8262 option 1 and option 2 compliance
GNSS and Time
• Synchronization to 1PPS input
• Support for NMEA-0183UART

DS0142应用:

• Integrated base station reference synchronization for the following air interfaces:
• GSM, WCDMA, TD-SCDMA, LTE and LTE-A
• FDD or TDD mobile technology
• Femto cells, small cells (residential, urban, rural, enterprise), pico cells and macro cells
• Mobile Backhaul NID, cell-site router, edge switch/router, microwave or access aggregation node
• EPON/GPON OLT and ONU/OLT
• DSLAM and RT-DSLAM
• Data Center: top-of-rack switches, server blades

图1. DS0142框图

图2. DS0142IEEE 1588定时同步模块应用架构图

图3. DS0142软件架构图

图4. DS0142IEEE 1588定时同步模块电路图(1)

图5. DS0142IEEE 1588定时同步模块电路图(2)

图6. DS0142IEEE 1588定时同步模块电路图(3)

图7. DS0142IEEE 1588定时同步模块电路图(4)

图8. DS0142IEEE 1588定时同步模块电路图(5)

图9. DS0142IEEE 1588定时同步模块电路图(6)

图10. DS0142IEEE 1588定时同步模块电路图(7)

图11. DS0142IEEE 1588定时同步模块电路图(8)

图12. DS0142IEEE 1588定时同步模块电路图(9)
详情请见:
https://www.microsemi.com/products/fpga-soc/design-resources/dev-kits/smartfusion2/ieee-1588-module#documentation
https://www.renesas.com/zh-cn/doc/products/mpumcu/doc/rx_family/r20ut3558eg0100-rsk+rx65n-usermanual.pdf
Microsemi_IEEE_1588_Timing_Synchronization_Module_Datasheet_DS0142_V1.pdf
MICROSEMI_IEEE_1588_TIMING_SYNCHRONIZATION_MODULE_SCH_11-17-17.pdf

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